Responsibilities:
1. Design and verify pre- and post-layout mixed-signal circuits (block and/or chip level).
2. Provide guidance and feedback to layout engineers.
3. Plan and implement testability of the circuits.
4. Perform cost/power/performance optimization with system engineers.
Required Skills and Qualifications:
1. MSEE with 8+years or PhD with 6+ years of related industry experience.
2. Experience with complete design cycle from definition to product release.
3. Ground-up design experience with more than one of the following blocks: LDO, signal detector, high-speed amplifier, ADC, DAC, fractional-N PLL, continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), and SRAM.
4. Good understanding of risks and their mitigation.
5. Good understanding of circuit non-idealities such as mismatch, noise and nonlinearity.
6. Good s-domain and/or z-domain analysis skills.
7. Good bench skills.
Preferred Skills and Qualifications:
1. Experience with full-duplex wireline communication systems (e.g. Ethernet).
2. Experience with layout-related effects in advanced CMOS processes.
3. Experience with automotive products.
4. Experience with SI/PI.
5. Experience with EMC/EMI.
6. Experience mentoring junior engineers.
Responsibilities:
1. Develop equalization adaptation algorithms for receiver CTLE, FFE and DFE.
2. Develop baud-rate timing recovery algorithm.
3. Perform link budget analysis and simulation.
4. Perform cost/power/performance optimization with design engineers
Required Skills and Qualifications:
1. MSEE with 8+years or PhD with 6+ years of related industry experience.
2. Strong s-domain and z-domain analysis skills.
3. Strong understanding of wireline communication systems, including the pros and cons of different equalization and timing recovery techniques.
4. Strong system and behavioral modeling skills.
5. Strong communication skills to transfer algorithms to the design team.
Preferred Skills and Qualifications:
1. Experience with full-duplex wireline communication systems (e.g. Ethernet).
2. Experience with ADC-based wireline link using PAM4 and beyond.
3. Experience with automotive applications.
4. Experience with SI/PI.
5. Experience with EMC/EMI.
6. Experience mentoring junior engineers.
7. Good silicon debug skills.
Responsibilities:
1. Responsible for the formulation of test plans and specifications, the development and verification of test procedures, the analysis of test data and the preparation of test report.
2. Responsible for handling abnormalities in the production process and customer feedback.
3. Undertake the research and development of component testing technology.
4. Formulate and implement product quality and reliability evaluation strategies and plans according to product characteristics.
5. Assist R&D to find and improve the quality and reliability defects of product design.
6. Risk mass production node control, dppm target management.
7. Failure analysis for product quality problems in the mass production line and market client feedback.
Requirements:
1.Bachelor's degree or above in related majors such as electronic technology or computer communication.
2.More than 3 years of experience in chip testing
3.Familiar with the structure and working principle of semiconductor devices, with basic analog and digital circuit design and analysis capabilities
4.Have basic circuit design, debugging ability, and master the operation method of basic circuit experimental instruments.
5.Proficient in a programming language: C, C++, VB, Python, Perl, etc.
6.Have good logical analysis ability, and be able to analyze, design and finally solve the problems encountered in an orderly manner.
7. Familiar with the principles and schemes of high-speed interface testing, such as SERDES, USB3.0, DP, etc. are preferred.
Responsibilities:
1.Committed to the design, simulation and implementation of the physical layer algorithm of wireless communication systems.
2.Responsible for the design of digital baseband algorithms, including AGC, synchronization, equalization, channel estimation, MIMO detection, DFE, RF calibration, channel encoding and decoding, etc.
3. Modeling and simulation of wireless channels.
4. Support the algorithm implementation and debuing of the chip.
Requirements:
1. Have studied the principles of wireless communication, digital signal processing, statistical signal processing, digital communication, information theory and coding.
2. Proficient in Matlab, C/C++ programming language.
3. Master's degree in EE, communication, microelectronics, computer, electromagnetic field and other related majors is preferred.
4. Experience in the design and development of baseband algorithms such as WIFI/Bluetooth/GNSS is preferred..
Responsibilities:
1. Responsible for IP-level or SOC system-level verification of high-speed interfaces (USB/UFS/PCIE/LPDDR, etc.).
2. Analyze system application scenarios, formulate detailed verification plans, and organize plan reviews; participate in the review of chip design documents as experts, and output effective opinions.
3. Plan the verification architecture and environment, use SV/UVM to build a verification environment or guide other engineers in environment construction and use case design, and be proficient in using VIP (Testsuit) to build verification use cases.
Requirements:
1. More than 3 years of digital chip verification experience, familiar with high-speed interface (USB/UFS/PCIE, etc.) standard protocols, familiar with system application scenarios.
2. Master's degree or above in microelectronics/communication/computer/automation/information.
3. Familiar with Verilog/SystemVerilog, UVM verification methodology or OOP development experience is preferred.
4. Familiar with AMBA, Low power and other related knowledge is preferred.
5. Familiar with Linux working environment, with Python/Perl scripts is preferred.
Responsibilities:
1. Formulate the company's sales strategy according to the company's development plan.
2. Analyze and investigate the target market, and formulate proposals for product research and development direction.
3. Responsible for the daily management within the department and the performance appraisal.
4. Visit key customers regularly to understand and deal with problems in a timely manne.
5 Responsible for regularly analyzing sales data, leading the team to develop new businesses, and continuously improving customer satisfaction.
Requirements:
1. Experience in the sales of vehicle gauge chips is preferred, and familiarity with Tier1/2 manufacturers and automotive mainframe manufacturers is preferred.
2. More than 8 years of sales experience in the semiconductor industry, bachelor's degree or above, majoring in microelectronics, electronic information and other related majors.
3. Strong business sense, which can promote the development of sales projects in a relatively complex environment.
4. Have comprehensive knowledge of semiconductor products, rich domestic market and domestic customer resources.
5. Results-oriented, with good communication skills, excellent leadership, team building and management skills.
Responsibilities:
1. Establish and maintain the company's quality management system and ensure effective operation.
2. Carry out project quality planning and formulate quality assurance plans for business needs.
3. Responsible for the review and inspection of the project, and responsible for the review of project issues.
4. Provide training, advice and guidance to the project team on development processes and tools.
Requirements:
1. Bachelor degree or above, major in science and engineering.
2. More than five years of quality management experience and supplier management experience in the integrated circuit industry.
3. Familiar with the test specifications and procedures of vehicle gauge chips..
4. Have led the chip AEC-Q100, ISO26262 certified test projects, and have experience in chip project quality management.
5. Experience in car chip enterprises is preferred (such as NXP, TI, ADI, Qualcomm, etc.).
6. Priority of PMP / CQE certificate.
Responsibilities:
1. Communicate with customers and marketing / application engineers to understand applications and contribute to architectural decisions for new products.
2. Determine technical feasibility, design methods and product specifications for new product development.
3. Architecture, specification, and design of blocks and subsystems in an SOC or mixed-signal AFE.
4. Establishes the entire data path from the system specification related to the precision converter filter architecture.
5. Establish various control circuits and communication ports.
6. The algorithm is developed with C / C + + / matlab in soft layer and DSP / MCU core firmware or RTL in hard layer.
7. Design validation using SystemVerilog and cosim methods in digital and mixed signal domains.
8. FPGA Development: Pre-silicon New Algorithms / Features, Post-silicon Debugging Platform.
Requirements:
1. Master degree or above in electronics, microelectronics or related major, solid basic knowledge of circuit.
2. Digital signal processing design experience.
3. Proficient in Verilog programming language, Cadence and other design tools, familiar with Linux / Unix operating system.
4. Familiar with digital IC design procedures, verification tools and methods (e.g. NC / VCS), proficient in scripting.
5. Understand the front-end / back-end design process.
Responsibilities:
1. Responsible for the design, simulation and verification of high-speed analog mixed signal circuits.
2. Design layout and instruct layout engineer to make layout design to meet the requirement of circuit design.
3. Responsible for behavioral modeling of the high - speed serial link system.
4. participate in the development of laboratory evaluation plan, and use laboratory test equipment for testing and evaluation of engineering samples, and possible chip debugging.
5. Assist test engineer to define and develop procedures for in-test and finished test specifications.
Requirements:
1. Master degree or above in Electronic Engineering with 5+ years relevant industry experience.
2. Extensive design experience in DFE or CDR .
3. Extensive design experience in DDR or other high-speed circuit designs (PCIe, HDMI, SerDes).
4. Good knowledge in the field of high-speed interface design.
5. Rich experience in silicon post-test and verification, good command of laboratory instruments (oscilloscope, network analyzer).
6. Instruct layout engineer to design layout to meet the requirements of circuit design.
7. Proficiency in deep submicron CMOS technology and device physics.
8. Skilled use EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc). Verilog, Verilog-A and/or Matlab.
Responsibilities:
1. Communicate with customers and marketing / application engineers to understand applications and contribute to architectural decisions for new products.
2. Determine technical feasibility, design methods and product specifications for new product development.
3. Architecture, specification, and design of blocks and subsystems in an SOC or mixed-signal AFE.
4. Establishes the entire data path from the system specification related to the precision converter filter architecture.
5. Establish various control circuits and communication ports.
6. The algorithm is developed with C / C + + / matlab in soft layer and DSP / MCU core firmware or RTL in hard layer.
7. Design validation using SystemVerilog and cosim methods in digital and mixed signal domains.
8. FPGA Development: Pre-silicon New Algorithms / Features, Post-silicon Debugging Platform.
Requirements:
1. Master degree or above in electronics, microelectronics or related major, solid basic knowledge of circuit.
2. Digital signal processing design experience.
3. Proficient in Verilog programming language, Cadence and other design tools, familiar with Linux / Unix operating system.
4. Familiar with digital IC design procedures, verification tools and methods (e.g. NC / VCS), proficient in scripting.
5. Understand the front-end / back-end design process.